Phase locked loops (or PLLs) are used to generate an output signal with a defined phase relationship to an input reference signal. The output signal is matched to the phase of the input reference signal by a feedback loop in which the phase difference between the input reference signal and the output signal is determined by a phase detector. In a digital phase locked loop, the phase detector outputs a digital signal. The output from the phase detector (indicating phase error) is received by a loop filter. The loop filter in turn provides an output signal to a frequency controlled oscillator. In an all-digital phase locked loop, the phase detector may output a digital signal, the loop filter may be a digital loop filter, and the frequency controlled oscillator may be a digitally controlled oscillator.
Phase locked loops are often required to achieve a specific noise performance. The maximum allowable phase noise may be determined by an intended application for a phase locked loop.
Sources of phase noise in a phase locked loop may include: external oscillator noise (resulting from an imperfect reference oscillator signal); frequency controlled oscillator noise, and quantization noise, arising from quantization of the phase error at the phase detector.
A phase locked loop with reduced noise is desirable.